Display devices including an active matrix substrate that includes a switching element for each of pixels are in wide use. An active matrix substrate including a thin film transistor (hereinafter, referred to as a “TFT”) as a switching element is called a “TFT substrate”. In this specification, a part of such a TFT substrate corresponding to a pixel of the display device may also be referred to as a “pixel”.
A TFT substrate usable for a liquid crystal display device or the like includes, for example, a glass substrate, a plurality of TFTs supported by the glass substrate, gate lines and source lines, and pixel electrodes arrayed in a matrix. A gate electrode of each of the TFTs is electrically connected with a corresponding gate line, a source electrode of each TFT is electrically connected with a corresponding source line, and a drain electrode of each TFT is electrically connected with a corresponding pixel electrode. Usually, the TFTs, the source lines and the gate lines are covered with an interlayer insulating layer, and the pixel electrodes are provided on the interlayer insulating layer and are each connected with a drain electrode of a corresponding TFT in a contact hole formed in the interlayer insulating layer.
As the interlayer insulating layer, an insulating layer formed of an organic insulating material (such an insulating layer is occasionally referred to as an “organic insulating layer”) may be used. For example, patent documents 1 and 2 each disclose a TFT substrate including an inorganic insulating layer and an organic insulating layer formed thereon which act together as an interlayer insulating layer covering the TFTs and the lines. An organic insulating material has a dielectric constant lower than that of an inorganic insulating material and tends to be thick when being formed into a layer. Even if an interlayer insulating layer including a relatively thick organic insulating layer (having a thickness of, for example, about 1 μm to 3 μm) is formed and is located such that a peripheral region of the pixel electrode overlaps the gate line and/or the source line with the interlayer insulating layer being provided therebetween, the pixel electrode and the gate line and/or the source line have a small parasitic capacitance formed therebetween. This allows the pixel electrode to be located so as to overlap the gate line or the source line. As compared with the case where the pixel electrode is located so as not to overlap the lines, the numerical apertures of the pixels is improved.